[Icc-mot] uexec and XGATE chip

[Edward Karpicz]

Oops, fixing myself:

clr  1.-sp
----------
= 2 bytes, 1 bus cycle

clra
psha
-----------
= 2 bytes, 2 bus cycles

ldaa  #0
psha
--------------
= 3 bytes, 2 bus cycles


sorry for noise

Edward



----- Original Message ----- 
From: "Edward Karpicz" <ekarpicz at freemail.lt>
To: "Discussion List for ICC08/11/12/16 users. You do NOT need 
tosubscribetoicc-announce if you are a member of this." 
<icc-mot at imagecraft.com>
Sent: Monday, October 08, 2007 1:51 PM
Subject: Re: [Icc-mot] uexec and XGATE chip


> Hi
>
> I'm glad you made it working. But "clr  1,-sp" would be nicer :-), just 2 
> cycles and 2 bytes. clra+psha takes 3 bus cycles.
>
> Regards
> Edward
>
>
> Peter Lissenburg wrote:
>> Hi Edward,
>> with
>> ldaa #0
>> psha
>> in those places you pointed out and all works fine.
>> Now to keep my eyes open for other differences.
>>
>> Thanks for your help.
>> Peter L.
>>
>>
>>
>> Peter Lissenburg wrote:
>>> Hi Edward,
>>>     thanks for that, important point I had missed, although I should 
>>> have questioned the extra stuff NoIce was showing me.
>>> Before the
>>> CLR 1,-SP
>>> should I not make another entry to modify? by
>>> psha
>>> ?
>>>
>>> I'll have a go and learn more....
>>> Thanks.
>>> Peter L.
>>>
>>>
>>>
>>> Edward Karpicz wrote:
>>>> Peter Lissenburg wrote:
>>>>
>>>>> Hi Richard and all,
>>>>> I'm starting to use the uexec code on an xgate chip. Finding a 
>>>>> problem(s),
>>>>> that I have not tracked down yet, so I thought I'd ask if anyone has 
>>>>> done
>>>>> this and solved this (unknown as yet!) problem.
>>>>> Thanks for any insights.
>>>>> Peter L.
>>>>>
>>>>>
>>>>
>>>> Hi Peter,
>>>>
>>>> S12X CCR is 16bits wide, while S12 CCR is 8bits wide. As a result 
>>>> interrupt stack frames do differ. This doesn't hurt anybody except when 
>>>> code has to manipulate interrupt stack frame. I found two "suspect 
>>>> places" in hc12.s file from examples12\uexec_dp256.zip, please search 
>>>> for "create an interrupt stack frame":
>>>>
>>>> ...
>>>> _UEXC_SavregsAndResched::
>>>> ; first create an interrupt stack frame
>>>> pshy
>>>> pshx
>>>> pshd  ; what a concept, not A:B
>>>> tpa
>>>> anda #0xEF ; re-enable interrupt when it "returns" since
>>>> psha  ; Defer() disables interrupt
>>>> ...
>>>>
>>>> In bottom three lines 8bit CCR is pushed to the stack. CCRh should be 
>>>> pushed next. CCRh holds interrupt priority level and it should be zero 
>>>> for foreground tasks. So add CLR 1,-SP after psha and it should get 
>>>> ported, I think.
>>>>
>>>> ...
>>>> _UEXC_SavregsAndResched::
>>>> ; first create an interrupt stack frame
>>>> pshy
>>>> pshx
>>>> pshd  ; what a concept, not A:B
>>>> tpa
>>>> anda #0xEF ; re-enable interrupt when it "returns" since
>>>> psha  ; Defer() disables interrupt
>>>>   CLR   1,-SP
>>>> ...
>>>>
>>>> ...
>>>> _UEXC_StartNewTask::
>>>> lds _uexc_current_sp
>>>> ; make KillSelf as the "return pc" of a new task, so if it
>>>> ; ever returns, it will reclaim the storage
>>>> ldd #_UEXC_KillSelf
>>>> pshb
>>>> psha
>>>> ldd _uexc_current_func
>>>> pshb
>>>> psha
>>>> ; create an interrupt stack frame
>>>> pshy
>>>> pshx
>>>> pshd
>>>> tpa
>>>> anda #0xEF ; re-enable interrupt
>>>> psha  ;
>>>>   CLR   1,-SP
>>>> ...
>>>>
>>>>
>>>> Regards
>>>> Edward
>>>>
>>>> _______________________________________________
>>>> Icc-mot mailing list
>>>> Icc-mot at imagecraft.com
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>>>>
>>>>
>>>>
>>>
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>>>
>>
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