[Icc-mot] XGate asm and S12X GPAGE support

[Edward Karpicz]

Richard wrote:

> The Xgate capable asm is ready for beta testing:
> http://www.dragonsgate.net/pub/BETAS/ias6812w.exe Put it in your 
> c:\iccv712\bin\ directory after saving the previous one. The directive
>
> .CPU XGATE
> .CPU S12


First problem

    .CPU XGATE doesn't work if XGATE is in capital letters.

.CPU xgate
  or
.cpu  xgate

are fine.

Another problem. While is S12 mode, doesn't compile

   BSET  RDRS,#8+2

!E : invalid registrer

and RDRS is Reduced Drive poRt S register. Assembler probably mixed RDRS 
with some xgate Rx register?


Anyway I'll try to make some xgate code working today.


>
> switches between the two instruction set. A ".CPU S12X" will be added 
> later for S12X support. This will probably be the extent of ICC12 XGate 
> support for a while. It's not clear whether we will support the XGate in C 
> level.
>
> For the S12X GPAGE support, I am considering the following proposal:
> - program code will continue to use the S12 style PPAGE paging with 
> CALL/RTC (e.g. no change)
> - A new "GPAGE data access" will be supported. All data must fit within a 
> single 64K page and data addresses are 16 bits offset within this page. At 
> startup, GPAGE register is initialized to point this page. Compiler will 
> use Gld/Gst for all data accesses.

Nice idea. If not everything GPAGE accessible then at least very comfortable 
access to 64k of data. Comfortable because no need to care about GPAGE. 
Single GPAGE it's either all available onchip RAM or 64k of flash.

Edward


>
> I think this should be sufficient for most users without going to the pain 
> of data paging. Comments? Suggestions?
>
> // richard <http://www.imagecraft.com> 
> <http://www.dragonsgate.net/mailman/listinfo>
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