I think this is the one your talking about:<br><a href="http://www.atmel.com/dyn/resources/prod_documents/doc2564.pdf">http://www.atmel.com/dyn/resources/prod_documents/doc2564.pdf</a><br><br><br><div><span class="gmail_quote">
On 6/5/07, <b class="gmail_sendername">John Baraclough</b> <<a href="mailto:j_baraclough@zetnet.co.uk">j_baraclough@zetnet.co.uk</a>> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
The only limitation I'm aware of in the TWI is that the CPU clock<br>must be at least 16x the TWI bit rate in slave mode. In master mode,<br>the setting of TWBR depends on the slowest external slave device on<br>the I2C bus. It would help to know of which application note you are thinking.
<br><br>All the best for now,<br>John<br><br><br>At 12:19 05/06/2007, you wrote:<br>>I have seen in an application note that the TWBR register must not be set to<br>>less than 10.<br>><br>>There is no mention of this limitation in the Mega2560 data sheet that I can
<br>>see; does anyone know if is it still valid ?<br>><br>>Regards<br>><br>>Andy<br>><br>><br>>_______________________________________________<br>>Icc-avr mailing list<br>><a href="mailto:Icc-avr@imagecraft.com">
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