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OK, I've got it now. I notice that the app. note is dated September 2004
and doesn't give any reason for that minimum setting. It also states that
the prescalar bits in the status register should be set to zero, which is
really strange.<br><br>
The only reason I can think of for requiring a minimum of 10 CPU clocks
for each cycle of SCL is to allow the CPU to execute some cycles after
the start condition is transmitted and before the interrupt occurs. I
can't think of any good reason for not using the prescalar.<br><br>
Anyway I've put a question on comp.arch.embedded as there are a couple of
Atmel employees who lurk there and occasionally answer
questions.<br><br>
All the best for now,<br>
John<br><br>
<br>
At 18:36 05/06/2007, you wrote:<br>
<blockquote type=cite class=cite cite="">I think this is the one your
talking about:<br>
<a href="http://www.atmel.com/dyn/resources/prod_documents/doc2564.pdf">
http://www.atmel.com/dyn/resources/prod_documents/doc2564.pdf</a><br><br>
<br>
On 6/5/07, <b>John Baraclough</b>
<<a href="mailto:j_baraclough@zetnet.co.uk">
j_baraclough@zetnet.co.uk</a>> wrote:<br>
<dl>
<dd>The only limitation I'm aware of in the TWI is that the CPU
clock<br>
<dd>must be at least 16x the TWI bit rate in slave mode. In master
mode,<br>
<dd>the setting of TWBR depends on the slowest external slave device
on<br>
<dd>the I2C bus. It would help to know of which application note you are
thinking. <br><br>
<dd>All the best for now,<br>
<dd>John<br><br>
<br>
<dd>At 12:19 05/06/2007, you wrote:<br>
<dd>>I have seen in an application note that the TWBR register must
not be set to<br>
<dd>>less than 10.<br>
<dd>><br>
<dd>>There is no mention of this limitation in the Mega2560 data sheet
that I can <br>
<dd>>see; does anyone know if is it still valid ?<br>
<dd>><br>
<dd>>Regards<br>
<dd>><br>
<dd>>Andy<br>
<dd>><br>
<dd>><br>
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<br>
-- <br>
Paul Mateer, AA9GG<br>
Elan Engineering Corp.<br>
<a href="http://www.elanengr.com">www.elanengr.com</a> <br>
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