SV: SV: SV: [Icc-avr] Debug using Jtag

[Steven Lose]

Hi John.

 

Thanks a lot for offering your help.

I try a bit more before I start crying in your mailbox.

 

That's how my mail started and I wrote a whole lot more before the 10cent hit me... hard. Still hurts.

 

This product have something all the other products using this uart code don't have.

A  heavily loaded cpu, and as I already have testet, the TXC is called before tx is complete.

Meaning that the TXC flag is just standing there waiting for UDRE to fill the last byte in, leaving the data index pointer on the NrOfBytesToSend value

And TXC is executed a uSec later.

 

After 5 days of debug, it's getting difficult to sort out the results of all the tests I've made.

 

As you said, clear the flag for every UDRE interrupt. Obvious.

Where shall I send the T-shirt?

 

Then it's going to be a nice weekend anyway, thanks a lot.

Have a very nice weekend, and to all others too.

 

By the way, datasheet says:

The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit

Shift Register has been shifted out and there are no new data currently present in the

transmit buffer.

 

 

 

Med venlig hilsen / Best regards / mit freundlichen Grüßen

EC POWER A/S

Steven Lose

Software Ingeniør

Tlf.: +45 87434100

Direkte tlf. +45 58286608

Email: sl at ecpower.dk <blocked::mailto:bsl at ecpower.dk> 

www.ecpower.dk

________________________________

Fra: icc-avr-bounces at imagecraft.com [mailto:icc-avr-bounces at imagecraft.com] På vegne af John Baraclough
Sendt: 28. september 2007 12:26
Til: Discussion list for ICCAVR and ICCtiny Users. You do NOT need tosubscribe to icc-announce if you are a member of this.
Emne: Re: SV: SV: [Icc-avr] Debug using Jtag

 

Hi Steven,

Yes, that's a tricky one. The TXC interrupt flag is set every time a complete character is transmitted, regardless of whether there is another character waiting in the buffer. What you have to do is clear the TXC flag every time you hit the UDRE interrupt and only enable the TXC interrupt in the UDRE interrupt handler once there are no more characters to be sent. As the RS485 can be switched very quickly, it is also a good idea to add an extra stop bit to the last transmitted character.

You're welcome to contact me directly if you need any more help.

All the best for now,
John


At 10:26 28/09/2007, you wrote:



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Hi.
 
I got a little further, and found out that The write seems to be the legal function anyway, I just didn't caught it because TXC complete int. is getting served before the Tx Buffer is empty.
 
In 0.003% of the transmissions, as soon as the UDRE interrupt is finished filling the last bytes in Txbuffer and disables itself, TXC int is served before buffer is finished transmitting.
 
Result is that the last or the 2 last bytes in Txbuffer is not transmitted because TXC sets the RS485 driver back in Input mode.
 
So now I just have to find out why!
It's nothing but fun.
 
Med venlig hilsen / Best regards / mit freundlichen Grüßen
 
EC POWER A/S
 
Steven Lose
 
Software Ingeniør
 
Tlf.: +45 87434100
 
Direkte tlf. +45 58286608
 
Email: sl at ecpower.dk
 
www.ecpower.dk <http://www.ecpower.dk/>  

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