[Icc-avr] Optimization of write and read to register STS, LDS

[Richard]

val_1 being the same as "1" will/should be caught by MIO (PRO).

This optimization looks doable, probably will only add it to the PRO 
version though... Thanks for the suggestion...

At 11:35 AM 10/1/2007, Bengt Ragnemalm wrote:
>Richard, as this is a post for optimization I think this is most for you.
>
>I post the code here so I can describe how this optimization works. What I
>ask is if this type of optimization is or can be done by the compiler. When
>there is always the question of how much effect it will have.
>
>-----
>Assembler snippet:
>RETRO_CAL: STS  CLKPR,V128  ;DROP CLOCK TO 1Mhz
>            STS  CLKPR,THREE ;
>            STS  TIMSK1,ZERO ;SETUP TIMER1
>            STS  TCCR1B,ONE  ;TC1 = 1MHz = 1uS
>            STS  TIMSK2,ZERO ;SETUP TIMER2
>            STS  ASSR,EIGHT  ;CLOCK FROM 32KHz OSCILLATOR
>            LDI  TMP1,200    ;OCR2A = 200
>            STS  OCR2A,TMP1  ;200 / 32768Hz ~= 6103uS
>            STS  TCCR2A,ONE  ;TC2 = 32768Hz ~= 30.5176uS
>            LDS  TMP,OSCCAL  ;READ OSCCAL
>----
>Same snippet in C:
>void OSCCAL_retrocal(void)
>{
>     unsigned char temp;
>     unsigned char val_1 = 0x01;
>     unsigned char low,high;
>     // set the CPU Frequency to 1MHz (8Mhz / 8 = 1Mhz)
>     CLKPR   = (1<<CLKPCE);
>     CLKPR   = (1<<CLKPS1)|(1<<CLKPS0);
>     // setup timer1 TC1= 1MHz = 1usec
>     TIMSK1  = 0;
>     TCCR1B  = val_1;
>     // setup timer2
>     TIMSK2  = 0;
>     // set 32,768kHz osc as source for timer2
>     ASSR    = (1<<AS2);
>     // 200 / 32768Hz ~= 6103uS
>     OCR2A   = 200;
>     // TC2 = 32768Hz ~= 30.5176uS
>     TCCR2A  = val_1;
>     temp = OSCCAL;
>----
>You can see that there are several registers acesses that is done with STS
>or LDS instructions. As there are so many of them someone suggested that
>they were replaced with STD and LDD instructions. To use displacement I
>understand that the Z register (?) must be used. Also the loading of the Z
>register will cost some bytes extra. Maybe the Z register is already in use
>and in that case this possibility can only occur in very special moment
>making it not worth the effort.
>
>But I like to stretch C and the compiler to its limits to see how far you
>can go before you have to switch to inline assembler.
>
>Also note the lokal variable val_1 that is used to set the value 1 several
>times.
>
>Regards
>Bengt
>
>
>-------------------
> > I am testing a size optimized osccal routine (RetroDan, AVRfreaks). It is
>a
> > hint there about the possibility to optimize many STS and LDS
>instructions
> > with LDD and STD (load and store with displacement).
> >
> > It occured to me that why could a C-compiler not catch that possibility?
>Or
> > maybe it would be possible to "fool" the compiler to use it anyway.
> >
> > Regards,
> > Bengt

// richard (This email is for mailing lists. To reach me directly, 
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